Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the semiconductor device. In particular, embodiments of the present invention relate to superjunction semiconductor devices having narrow surface layout of terminal structures, buried contact regions and trench gates, and methods for manufacturing the devices.
Since the invention of superjunction devices by Dr. Xingbi Chen, as disclosed in U.S. Pat. No. 5,216,275, the contents of which are incorporated by reference herein, there have been many attempts to expand and improve on the superjunction effect of his invention. U.S. Pat. Nos. 6,410,958, 6,300,171 and 6,307,246 are examples of such efforts and are incorporated herein by reference.
Trench-type superjunction devices are expected to replace multi-epi superjunction devices because of the potential lower processing cost. FIG. 1 illustrates an enlarged partial cross-sectional view of a trench-type superjunction device that includes a semiconductor substrate 10 having a substrate region 3 and a semiconductor material layer 5 at two opposed surfaces 2, 4 of the semiconductor substrate. The semiconductor material layer 5 includes a plurality of trenches 7, which are filled with a semi-insulating material and/or an insulating material 8, and a plurality of mesas 9, each of which has alternating p and n columns 11 and 13, respectively.
Superjunction devices, including, but not limited to metal-oxide-semiconductor field-effect transistors (MOSFET), diodes, and insulated-gate bipolar transistors (IGBT), have been employed in various applications such as automobile electrical systems, power supplies, and power management applications. Such devices sustain high voltages in the off-state and yield low voltages and high saturation current densities in the on-state.
It is known that cell density is important for the performance of a semiconductor device. In the case of a low voltage MOSFET, cell density is directly related to the MOSFET channel density, and the channel density dominates the on-resistance of the MOSFET. In the case of high voltage devices, on-resistance is subject to the influence of the drift region, e.g., column 13 in FIG. 1. When a mesa/trench becomes narrower, channel density and drift region density increase. Because a trench acts as a “dead space”, increasing channel density alone does not improve the on-resistance of the high voltage device. In addition, the narrower mesa of a high voltage device can be pinched off more readily.
In the case of high voltage superjunction devices, the mesas can be doped with increasing amounts of one or more dopants when mesa/trench width is narrowed. The increasing amounts of dopants allow the narrower mesas to sustain higher voltage without being pinched off. Therefore, the combination of increased cell density and increased doping concentration helps to reduce the on-resistance for a superjunction device, allowing the device to accommodate a higher density of current at high voltage. For example, in the case of the trench-type superjunction device illustrated in FIG. 1, the narrower the width of the mesas 9, the greater the number of the p and n columns 11, 13 per unit area, and the more current the device can accommodate. Therefore, for high voltage superjunction devices, it is desirable to reduce the width of the mesas 9 to pack as many p and n columns 11, 13 as possible per unit area. The same mechanism also applies to multiple epi superjunction devices.
Although narrower mesas can be readily achieved by adjusting the width of adjacent trenches and the diffusion process for the sidewall surfaces of the trenches during manufacture of a trench-type superjunction device, further reduction of the mesa width is restricted by the surface layout of the terminal structures for the device. Like most field-effect transistors (FETs), a superjunction semiconductor device can have four terminals, known as the gate, drain, source, and body/base, with the body and the source generally connected internally to simplify the design.
FIG. 2 is an enlarged partial cross-sectional view of a trench-type superjunction MOSFET having a unit cellular structure comprising pnp columns and a planar gate electrode 19 according to the prior art. The unit cellular structure of semiconductor substrate 10 comprises two filled trenches 7 flanking a mesa 9, which comprises alternating p, n, and p columns 11, 13, and 11, respectively. The semiconductor substrate 10 is connected to a drain electrode 15 and a source electrode 17, and is adjacent to a planar gate electrode 19. The drain electrode 15, as shown, is connected to the substrate region 3 at the exposed main surface 4. The source electrode 17 and the gate electrode 19, as shown, are located proximate the opposed main surface 2. The source electrode 17 is connected to source regions 27 and body contact regions 25 at the main surface 2. The source regions 27 and body contact regions 25 are each laterally connected to one another and extend from the main surface 2 to a shallow depth in body regions 23. The source regions 27 and the body contact regions 25 are highly doped with opposite conductivity types, such as n and p-type, respectively, in order to reduce the contact resistance. The body regions 23, having a p-type conductivity type, are connected to the p columns 11, separating the source regions 27 from the n column 13, and proximate the planar gate electrode 19, which is disposed over the main surface 2 with a gate dielectric layer 21 interposed between.
It is readily apparent that the width 29 of the mesa 9 is restricted by factors such as the width of the planar gate electrode 19 and the lateral distance 31 between the gate electrode 19 and the source electrode 17. The lateral distance 31 is generally limited by the width of the source regions 27 and the width of the body contact regions 25. Ideally, self-aligned contact technologies have been used to form the electrical contacts between the semiconductor device and the terminals, such as the gate 19, the source 17, and the drain 15. Drastic reduction in the size of one or more terminal structures, such as the width of the gate electrode 19, the source regions 27, the body regions 23, and/or the body contact regions 25, can potentially impact the performance of the device. For example, when the channel density is increased by narrowing the width of the source regions 27 or the body contact regions 25, contact resistance is increased, resulting in parasitic npn turn-on, consequently destroying the device.
The width 29 of the mesa 9 can be further narrowed by reducing the width of the gate electrode 19, i.e., by using a trench gate. Instead of using a planar gate electrode as shown in FIG. 2, a trench gate 19 is disposed in a gate opening extending from main surface 2 into mesa 9 toward the main surface 4 to a shallow depth position. The gate opening is further filled with a gate dielectric that separates the gate electrode 19 from the n column 13, the source regions 27, and the body regions 23. Such trench gates structures can still suffer from operational drawbacks resulting from the narrowing.
Therefore, it is desirable to provide narrow surface layouts of the terminal structures for a superjunction semiconductor device that allow reduction of the column width, thus further increasing the current density, and a method for manufacturing such device.